FIELD OF THE INVENTION
The invention relates to a synchronous integrated memory.
Synchronous memories are distinguished by the fact that data to be written are fed synchronously with an external clock signal and data to be read are output synchronously with the external clock signal. The processing within the memory often takes place with an internal clock signal that differs from the external clock signal. Data to be transferred are usually resynchronized from the external clock signal to the internal clock signal, or vice versa, directly at data connections of the memory, via which data connections the data are received from outside the memory or are output to outside the memory. For this purpose, corresponding synchronizing units are disposed directly adjacent to the data connections. In the event of a write access to the memory, data which are to be written and arrive externally at the data connections synchronously with the external clock signal are resynchronized with the internal clock signal by the synchronizing units before they are fed on corresponding data buses to a cell array within the memory, in order to be stored in memory cells.
The external connections of the memory and thus also its data connections are usually disposed in edge regions of the memory. In the event of a write access, a data bit to be written is transferred from each data connection to the corresponding cell array, in order to be stored there. Since the distances between the individual data connections and the cell array are generally different, the data signals that are communicated in the event of the write access experience propagation delay differences between the various data connections, where the signals are synchronized with the internal clock signal, and the cell array. These propagation delay differences become increasingly apparent at high clock frequencies, which are sought in particular for future memories.